Timings are in memory clock cycles. True latency in nanoseconds is derived from the data rate.
First-word latency (CL)
10.00 ns
Time from a read command to the first bit of data arriving.
I/O bus clock
3000 MHz
Cycle time
0.333 ns
tRCD delay
12.67 ns
tRP delay
12.67 ns
tRAS
26.00 ns
tRC (tRP + tRAS)
38.67 ns
Assumes one 64-bit channel. Dual channel doubles this, quad channel quadruples it.