TechCompare - RAM Latency Calculator (Embed)

Preset

Data rate

MT/s

CL (tCL)

clk

tRCD

clk

tRP

clk

tRAS

clk

Timings are in memory clock cycles. True latency in nanoseconds is derived from the data rate.

True Latency

First-word latency (CL)

10.00 ns

Time from a read command to the first bit of data arriving.

I/O bus clock

3000 MHz

Cycle time

0.333 ns

tRCD delay

12.67 ns

tRP delay

12.67 ns

tRAS

26.00 ns

tRC (tRP + tRAS)

38.67 ns

Peak bandwidth per channel48.0 GB/s

Assumes one 64-bit channel. Dual channel doubles this, quad channel quadruples it.

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Preset

Data rate

MT/s

CL (tCL)

clk

tRCD

clk

tRP

clk

tRAS

clk

Timings are in memory clock cycles. True latency in nanoseconds is derived from the data rate.

True Latency

First-word latency (CL)

10.00 ns

Time from a read command to the first bit of data arriving.

I/O bus clock

3000 MHz

Cycle time

0.333 ns

tRCD delay

12.67 ns

tRP delay

12.67 ns

tRAS

26.00 ns

tRC (tRP + tRAS)

38.67 ns

Peak bandwidth per channel48.0 GB/s

Assumes one 64-bit channel. Dual channel doubles this, quad channel quadruples it.