Reading 30-38-38-78
Kits print their timings as a string of numbers, like 30-38-38-78 on a DDR5-6000 kit. The order is CL, tRCD, tRP and tRAS, and all four count clock cycles. The fourth is often left off, and some labels add a fifth, the command rate, written 1T, 2T or CR2.
A smaller number means less waiting, but only against kits at the same data rate, since the length of a cycle depends on the speed. Cycles turn into nanoseconds the same way for every timing.
What each timing waits for
Memory chips store data in a grid of rows and columns. To read from a row, the chip first activates it, then reads a column, and later closes the row with a precharge. Each timing covers one of those steps:
- CL: the wait between the column address and the first data. 10.0 ns at 30 cycles on DDR5-6000.
- tRCD: the minimum wait between opening a row and reading its columns. 12.7 ns at 38 cycles.
- tRP: the minimum wait between a precharge command and opening the next row. 12.7 ns at 38 cycles.
- tRAS: the minimum time a row stays open before it can be closed. 26.0 ns at 78 cycles.
A fifth number is worked out, not printed. The row cycle time, tRC, is at least tRAS plus tRP. For this kit that's 38.7 ns.
Why a wrong row costs more
The timings add up differently depending on what's open. When the row you want is already open, the wait is CL alone, 10.0 ns. If no row is open, the chip needs tRCD first. If a different row is open, it has to close that one with tRP, open yours with tRCD, and then wait CL. On DDR5-6000 CL30-38-38 that's tRP plus tRCD plus CL, or about 35 ns in all.
So CL is the best case. How often a program finds its row already open depends on its access pattern. Programs access memory in different patterns, which is one reason tuning helps some programs and not others.
Tighter isn't always better
Two kits can trade timings. DDR5-6000 CL30-38-38-78 has the quicker CL, 10.0 ns against 12.0 ns for DDR5-6000 CL36-36-36-96, yet the CL36 kit opens a row in 12.0 ns against 12.7 ns. Its longer tRAS also stretches the row cycle time to 44.0 ns against 38.7 ns.
Compare the whole string, not CL alone, and judge it in nanoseconds. A kit's profile sets the other timings, and a BIOS can let you change them yourself, with a risk to stability.