What changed from DDR4
JEDEC published the DDR5 standard on July 14, 2020. Compared with DDR4, it changed these things:
- Voltage: 1.1 V, which is lower than DDR4.
- Speed: launch rates start at 4800 MT/s, where the standard DDR4 rates stop at 3200 MT/s.
- Burst length: 16 transfers per read, doubled from 8.
- Banks: 32 per chip, up from 16.
- Module layout: two independent subchannels on one module.
- Power: a voltage regulator on the module itself.
- Error correction: on-die ECC in every chip.
- Capacity: up to 512 GB per module, up from 64 GB.
On paper, DDR5-4800 peaks at 38.4 GB/s per channel against 25.6 GB/s for DDR4-3200, or 50% more. JEDEC has kept extending the standard since launch. Its 2021 update covers DRAM core timings up to 6400 MT/s, and its 2024 update extends the timing definitions to 8800 MT/s.
How a DDR5 module is built
A DDR4 module is one 64 bit channel. A DDR5 module is two independent subchannels, each with its own command bus and 32 data bits. Together they still add up to 64 bits, or 80 on an ECC module. The longer burst keeps each access at 64 bytes, the size of a CPU cache line, so the two halves can each take their own commands.
Power moved too. Voltage regulation went from the motherboard onto the module, where a power management chip (PMIC) makes the 1.1 V supply. Rambus says this gives better control of the power supply and helps signal integrity and noise.
Latency and what to buy
DDR5 wins on bandwidth, and latency depends on the kit. DDR5-4800 CL40 takes 16.7 ns against 10.0 ns for DDR4-3200 CL16, which is 67% more. Tuned DDR5 closes that gap. DDR5-6000 CL30 lands on the same 10.0 ns while peaking at 1.9 times the bandwidth of DDR4-3200.
A board takes one memory generation, so your CPU and motherboard decide whether DDR5 is an option at all. The DDR4 vs DDR5 comparison puts the tradeoff next to a build decision, and the DDR5-6000 CL30 page looks at a popular kit in detail.
Error correction on every chip
Every DDR5 chip has on-die ECC, which fixes errors inside the chip before data goes out. JEDEC lists it among the features that let chips be made on advanced process nodes. It isn't the same as ECC memory. The memory controller never sees it, and it doesn't protect the data on its way from the module to the CPU.