How ECC catches a flipped bit
A flipped bit is a stored 0 that reads back as 1, or the other way round. ECC memory stores extra check bits with every word, so the memory controller can spot one. The usual scheme is a Hamming type code called SECDED: single error correction, double error detection. It fixes any one bad bit in a word and flags two.
Through DDR4, a word is 72 bits wide, 64 data bits plus 8 check bits, and ECC modules usually have nine memory chips on each side. On DDR5 each of the two subchannels is 40 bits wide, 32 data and 8 check, for 80 bits per module. On every read the controller recomputes the code. Zero means no error. Anything else points to the bad bit, or tells the controller the error can't be fixed. Modern systems log both kinds, so a failing module shows up in the logs.
How often memory goes wrong
Google's large field study found that more than 8% of DIMMs were hit by errors in a year. It also found that hard errors, faults in the hardware itself, dominated over soft errors, and that temperature had a surprisingly small effect. Soft errors still happen. Wikipedia notes that most random ones in DRAM come from background radiation, mainly neutrons from cosmic ray secondaries, and the flux grows with altitude.
In a gaming PC, a flipped bit usually lands in data that's thrown away a moment later. In a file server, a database or a workstation that runs for weeks, it can land in data that gets saved and stays wrong. That's the case for ECC: long uptime, data you keep, and a cost for silent corruption. It costs more than normal memory and needs support from the CPU, the motherboard and the module, so check all three before you buy.
On-die ECC isn't ECC memory
Every DDR5 chip has on-die ECC, which fixes errors inside the chip before data goes out. But it adds no extra chips or data lines, and the memory controller can't see it. A normal DDR5 kit doesn't report corrections to your system, and nothing protects the data between the module and the CPU.
Full ECC memory, also called sideband ECC, sends the check bits along with the data and has the controller verify them. That protects the data end to end. MemTest86's ECC guide says full protection takes on-die ECC and sideband ECC used together. So a DDR5 kit isn't ECC memory just because DDR5 chips have on-die ECC.
Checking what you have
The CPU, the motherboard and the modules each have to list ECC support in their specs. To see it working, MemTest86 can read the ECC state, Linux reports memory errors through its EDAC subsystem, and Windows logs hardware errors through WHEA. A module that keeps logging corrected errors is a candidate for replacement.