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L1 vs L2 cache: how CPU cache tiers affect real-world performance

L1 cache is an order of magnitude faster than L2. Keeping your working set in L1 is the single biggest performance lever in CPU-bound code. But L2 hits are still excellent compared to RAM. Don't fear L2 misses. Fear RAM misses.

L1 cache is the fastest memory in a computer, typically 1 ns latency (3-5 CPU cycles) and 32-64 KB per core. L2 cache is slightly slower (3-4 ns, 10-15 cycles) but larger (256 KB to 1 MB per core). A program whose hot data fits in L1 runs dramatically faster than one that spills into L2, and L2 hits are still vastly faster than going to RAM.

By TechCompare · Updated

Hardware tier
CPU Cache
On-die processor cache levels
Topic focus
L1 vs L2 cache
l1-vs-l2
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How this is calculated

Modern CPUs use a multi-level cache hierarchy because faster memory is more expensive per byte and takes more die area. L1 is split into L1i (instructions) and L1d (data), each per-core and private. L2 is also per-core but unified (instructions and data together). L3 is shared across all cores on a chiplet or die. A miss in L1 that hits in L2 costs an extra 10-12 cycles. A miss that goes all the way to RAM costs 200+ cycles. This is why optimizing for cache locality (keeping data structures compact, accessing memory sequentially) can speed up a program by 10x or more.

Verdict

The numbers show why locality optimization pays off. L1d and L1i sit at roughly 1 ns (3-5 cycles) with 32-64 KB per core, while L2 runs 3-4 ns (10-15 cycles) at 256 KB to 1 MB. An L1 miss that hits L2 costs 10-12 extra cycles, but a miss that walks to RAM costs 200-plus. Compact, sequential data structures keep the working set in the fast tiers, which is why cache-friendly code can run 10x faster.

More Latency scenarios

L3 cache vs RAM
L3 cache (also called Last Level Cache or LLC) is shared across all cores in a CPU chiplet, typically 16-96 MB, with latency of 10-15 ns.
View details ➜
DDR4 vs DDR5 latency
DDR5 roughly doubles the peak bandwidth of DDR4 (from ~50 GB/s to ~100 GB/s per module), but true latency measured in nanoseconds is nearly unchanged.
View details ➜
NVMe vs SATA SSD
NVMe SSDs connect directly to the CPU over PCIe lanes, typically PCIe 4.0 x4 (8 GB/s) or PCIe 5.0 x4 (16 GB/s).
View details ➜

Related guides

CPU cache hierarchy
The hierarchy this L1 vs L2 comparison lives inside.
View guide ➜
Memory latency numbers
The full ladder these two cache tiers sit on.
View guide ➜

Frequently asked questions

What is the difference between L1 and L2 cache?
Speed versus size. L1 runs about 1 ns per access (3-5 CPU cycles) but holds only 32-64 KB per core, split into separate instruction and data halves. L2 is slower at 3-4 ns (10-15 cycles) but larger, at 256 KB to 1 MB per core, and unified. L1 is private and per-core. So is L2, while L3 is shared across cores.
How much slower is an L1 cache miss that hits L2?
About 10-12 extra cycles, so roughly 3-4x the L1 latency. That's survivable. The cliff comes when L2 misses too and the request walks to RAM, which costs 200+ cycles. The hierarchy exists precisely to keep most accesses in the tiers where a miss only costs a few cycles.
How do I write code that stays in L1 cache?
Keep hot data structures small and access them sequentially. Struct-of-arrays layouts and cache-line-sized chunks (64 bytes) let the prefetcher anticipate your next read. Linked lists and pointer-heavy structures scatter access across memory and miss constantly. Compilers can't fix layout for you, which is why data structure choice is the biggest lever in CPU-bound code.

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