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L3 cache vs RAM: the latency cliff and why it dominates server performance

If your working set fits in L3, you're fast. If it spills to RAM, you're 5x slower. Bigger L3 caches are one of the most cost-effective ways to improve real-world application performance, which is why AMD's 3D V-Cache parts dominate gaming benchmarks.

L3 cache (also called Last Level Cache or LLC) is shared across all cores in a CPU chiplet, typically 16-96 MB, with latency of 10-15 ns. RAM (DDR5) is 50-80 ns. The jump from L3 to RAM is roughly 5x in latency, which is the largest single step in the entire memory hierarchy. This is the cliff that performance engineers obsess over.

By TechCompare · Updated

Hardware tier
CPU Cache
On-die processor cache levels
Topic focus
L3 cache vs RAM
l3-vs-ram
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How this is calculated

A database index scan that fits in L3 runs 5x faster than one that spills to RAM. A game engine's texture streaming lives or dies on whether the working set stays in L3. Server CPUs (AMD EPYC, Intel Xeon) ship with massive L3 caches (up to 1 GB with 3D V-Cache) specifically because so many workloads are L3-bound. The L3-to-RAM gap is a physics problem: capacitance on the memory bus limits how fast signals can travel between the CPU die and the DIMM slots. 3D V-Cache stacks extra L3 directly on top of the CPU die to avoid the trip to RAM entirely.

Verdict

The hierarchy collapses at one specific jump. L3 runs 10-15 ns across 16-96 MB shared by every core, while DDR5 sits at 50-80 ns, so that one step costs 5x. Database scans and game texture streams live or die on whether the working set stays inside L3, which is why EPYC and Xeon ship L3 up to 1 GB and AMD stacks V-Cache directly on the die to skip the bus capacitance of the DIMM trip.

More Latency scenarios

L1 vs L2 cache
L1 cache is the fastest memory in a computer, typically 1 ns latency (3-5 CPU cycles) and 32-64 KB per core.
View details ➜
DDR4 vs DDR5 latency
DDR5 roughly doubles the peak bandwidth of DDR4 (from ~50 GB/s to ~100 GB/s per module), but true latency measured in nanoseconds is nearly unchanged.
View details ➜
NVMe vs SATA SSD
NVMe SSDs connect directly to the CPU over PCIe lanes, typically PCIe 4.0 x4 (8 GB/s) or PCIe 5.0 x4 (16 GB/s).
View details ➜

Related guides

L1 vs L2 cache
The cache tier upstream of this L3-vs-RAM cliff.
View guide ➜
DDR5-6000 CL30 latency
The specific DDR5 latency that L3-to-RAM misses cost the most.
View guide ➜

Frequently asked questions

How much slower is RAM than L3 cache?
About 5x. L3 sits around 10-15 ns per access while DDR5 RAM answers in 50-80 ns. That single step is the largest jump in the whole memory hierarchy, bigger than the L1-to-L2 step and far bigger than any SSD tier gap within storage. Keeping a working set inside L3 versus spilling to RAM is the difference between fast and visibly slow.
Why do Ryzen X3D chips with 3D V-Cache win gaming benchmarks?
Because games keep large, hot working sets for textures and world state, and V-Cache stacks extra L3 directly on the CPU die, up to 96 MB or more. A game whose working set fits in that enlarged L3 avoids the 50-80 ns trip to RAM, which shows up as measurably higher and more stable frame rates compared to the same chip without the stacked cache.
Why can't CPUs just have more L1 instead of an L3?
Physics and cost. Faster cache memory takes more die area per byte and draws more power, so a large L1 would be both expensive and slower by design trade-off. The hierarchy exists to fake 'large and fast' with 'small and fast on top of large and slow'. L1 gets the recent bytes, L2 catches its evictions, and L3 pools the rest across cores.

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